The present invention relates to a semiconductor integrated circuit device (IC) and, particularly, to a semiconductor IC capable of realizing desired functions by using a CAD automatic wiring technique.
Such a semiconductor IC includes a master slice type semiconductor IC which includes, for example, a memory such as ROM or RAM and functional blocks such as ALU, PLA and/or CPU. The semiconductor IC of this type will be referred to simply as a "composite semiconductor IC" hereinafter.
In the composite semiconductor IC, a multilevel wiring technique of a three-level metal wiring structure or more is employed with an increase in number of gates to be integrated on a single semiconductor chip. For example, T. Takahashi et al., "A 1.4M-Transistor CMOS Gate Array with 4 ns RAM", ISCC DIGEST OF TECHNICAL PAPER, p. 178-179, February 1989 discloses a gate array including 130K logic gates and eight 128 word.times.36 bit RAMs integrated on a 14.5.times.14.5 mm.sup.2 chip by use of a three-level metal wiring structure. Further, a gate array using a four-level metal wiring structure is disclosed in NIKKEI MICRODEVICES, p. 86 to 101, June 1989.
Function blocks included in a composite semiconductor IC are manually designed on the basis of a standard IC and arranged in a particular area of the chip of the composite semiconductor IC. Therefore, the integration density of an element of the function block is higher and the block can be realized with a smaller number of wiring layers compared with the master slice portion thereof. However, higher integration density of a function block means that the surface of the function block area of the semiconductor chip becomes uneven after an uppermost metal wiring is provided.
In order to improve the integration density of the composite semiconductor IC, it is preferable to provide a metal wiring used for the master slice portion further on the area of the function blocks of the semiconductor chip surface. In such a case, an inter-layer insulating film covering the function blocks is formed and the metal wiring is provided thereon. Since, however, the unevenness of the chip surface of the function block area is large, the step coverage, which is a ratio of minimum thickness of the metal wiring in a stepped portion to thickness of the wiring on the flat portion, is low and may deteriorate reliability. Further, the metal wiring formed on the function blocks through the inter-layer insulating film necessarily includes signal lines connected to circuits in the master slice portion, resulting in a cross-talk between the signal lines and signal lines of the function blocks which may cause a malfunction of the function blocks.